`include "define.v"
module MEM(
    input wire rst,
    input wire [5:0] op,
    input wire [31:0] regcData,
    input wire [4:0] regcAddr,
    input wire regcWr,
    input wire [31:0] memAddr_i,
    input wire [31:0] memData,
    input wire [31:0] rdData,
	input wire [31:0] hi,
	input wire [31:0] lo,
    output wire [4:0] regAddr,
    output wire regWr,
	output reg loWr,
	output reg hiWr,
	output wire [31:0] loData,
	output wire [31:0] hiData,
    output wire [31:0] regData,
    output wire [31:0] memAddr,
    output reg [31:0] wtData,
    output reg memWr,
    output reg memCe
);
assign regAddr = regcAddr;
assign regWr = regcWr;
assign regData = (op==`LW)?rdData:regcData;
assign memAddr = memAddr_i;
assign loData = lo;
assign hiData = hi;

always @(*)
    if(rst==`Enable)
    begin
        wtData = `Zero;
        memWr = `Disenable;
        memCe = `Disenable;
		loWr = `Disenable;
		hiWr = `Disenable;
    end
    else
        case(op)
        `LW:
        begin
            wtData = `Zero;
            memWr = `Disenable;
            memCe = `Enable;
			loWr = `Disenable;
			hiWr = `Disenable;
        end
        `SW:
        begin
            wtData = memData;
            memWr = `Enable;
            memCe = `Enable;
			loWr = `Disenable;
			hiWr = `Disenable;
        end
		`MULT:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			loWr = `Enable;
			hiWr = `Enable;
		end
		`MULTU:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			loWr = `Enable;
			hiWr = `Enable;
		end
		`DIV:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			loWr = `Enable;
			hiWr = `Enable;
		end
		`DIVU:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			loWr = `Enable;
			hiWr = `Enable;
		end
		`MTHI:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			hiWr = `Enable;
			loWr = `Disenable;
		end
		`MTLO:
		begin
        	wtData = `Zero;
        	memWr = `Disenable;
        	memCe = `Disenable;
			loWr = `Enable;
			hiWr = `Disenable;
		end
        default:
        begin
            wtData = `Zero;
            memWr = `Disenable;
            memCe = `Disenable;
			loWr = `Disenable;
			hiWr = `Disenable;
        end
        endcase
endmodule



